During the formation of a semiconductor device, particularly a nonvolatile memory device such as a NAND flash programmable read-only memory (flash PROM, or “flash device”), several structures are commonly formed. A typical flash device comprises various features as depicted in the plan view of FIG. 1, and the cross sections A-A and B-B of FIG. 1 depicted in FIGS. 2 and 3 respectively. FIGS. 1-3 depict a semiconductor wafer 10 comprising a first conductively doped region 12, for example a well region doped with a p-type dopant such as boron, and second doped regions 14, for example active area regions doped with an n-type dopant such as phosphorous or arsenic. The device may also comprise a plurality of transistors 16, 18, with transistors 16 providing memory gates and transistors 18 providing select gates for writing to and reading from the memory gates. Each transistor comprises tunnel oxide 20, a floating gate 22, intergate dielectric 24, a control gate (word line) 26, a capping dielectric layer 28 such as silicon nitride, and dielectric spacers 30 of silicon dioxide or silicon nitride. The doped wafer regions 12, 14 may be isolated from adjacent doped regions (not depicted) with shallow trench isolation (STI) structure 32. The FIGS. also depict one or more dielectric layers 34 such as tetraethyl orthosilicate (TEOS) and/or borophosphosilicate glass (BPSG), bit line (digit line) contacts 36 electrically coupled with one of the second doped regions 14, and bit lines (digit lines) 38. The manufacture and use of the device of FIGS. 1-3 is known in the art. An actual structure may comprise other elements not immediately germane to the present invention, and which have not been depicted for ease of explanation.
Another bit line design is depicted in FIG. 4 and sections C-C, D-D, and E-E of FIGS. 5, 6, and 7 respectively. Elements of the FIGS. numbered in accordance with the structures of FIGS. 1-3 have similar or identical functions as described for the design of FIGS. 1-3. The structure of FIGS. 4-7 has a reduced bit line contact height to width ratio (i.e. the “aspect ratio”) which must be etched for the bit line contacts over the method described in FIGS. 1-3. In addition, the structure of FIGS. 4-7 has reduced capacitance between the bit line and the gate due to thicker interlayer dielectric (ILD).
The structure of FIGS. 4-7, for example section E-E of FIG. 4 depicted in FIG. 7, illustrates a first bit line contact portion 70 and a second bit line contact portion 72 which are electrically connected by a conductive bit line contact interconnect 74. To form the structure, the first bit line contact portion 70 is formed, for example using a damascene contact process, then a polysilicon or metal layer is formed, masked, and etched to form the bit line contact interconnect 74. Another damascene process may then be used to form the second bit line contact portion 72 to contact the interconnect 74. While layer 34 depicts a single dielectric layer, this will in actuality comprise several different layers formed at different stages in the manufacturing process.
One problem which may occur during the formation of the structures of FIGS. 1-3 and 4-7 results from the small pitch between adjacent digit line contacts. These contacts are depicted as element 36 in FIG. 3 and 70 in FIG. 5. A continual goal of design and process engineers is miniaturization of device features. As processes improve to increase feature densities, the bit line contacts 36, 70 become smaller and closer together. As optical photolithography and etching processes are often pushed to their limits to maximize device densities and to reduce costs, bit line contacts may become increasingly susceptible to shorting with adjacent bit line contacts to result in a malfunctioning or nonfunctioning device. Replacement of one or more nonfunctional columns of transistors may be enabled with redundant columns, but this is a less than optimal solution which requires additional space on a semiconductor die.
One attempt to reduce the problem of shorted bit line contacts is depicted in the plan view of FIG. 8, and the sectional views across F-F and G-G depicted in FIGS. 9 and 10 respectively. With this design, adjacent bit line contacts are offset in an alternating pattern. As depicted in FIGS. 8 and 9, a first bit line contact portion 80 is formed within one or more layers of TEOS and/or BPSG 34, and a second bit line contact portion 82 is formed within one or more layers of TEOS and/or BPSG 84. The second bit line contact portion 82 is formed to be electrically coupled with the first bit line contact portion 80, and bit line 38 is formed to contact the second bit line contact portion 82. Thus the bit line portions 80, 82 provide an electrical pathway between the bit line 38 and one of the doped active area regions 14.
One problem with the design of FIGS. 8-10 is that the process requires several mask layers which have little processing latitude. A first mask must be used to etch the opening in layer 34 to receive the layer 80, a second mask must be used to etch the opening in layer 84 to receive layer 82, and a third mask must be used to etch the opening which receives layer 38. Additionally, the openings for layers 82 and 38 must be properly aligned with layer 80, which becomes more difficult with decreasing feature sizes and may be a cause of product failure and increase costs.
Further, as the distance between adjacent bit lines 38 decreases, the width of the bit lines must also decrease to ensure proper electrical isolation between columns of bit lines. With decreasing width, the resistance along the bit lines may increase beyond desirable levels which may contribute to device malfunction of failure. Wider bit lines are desired from an electrical standpoint to improve electrical characteristics, while narrower bit lines are desired to maximize device density. Additionally, the capacitive coupling between adjacent bit lines increases as the distance between them decreases. This increasing capacitance slows program and read performance due to increased times required for bit line precharge and discharge.
A method for forming a bit line contact, and a structure resulting from the method, which reduces or eliminates the problems described above would be desirable.
It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which may be determined by one of skill in the art by examination of the information herein.